1. Technical Field
This invention relates generally to semiconductor memory arrays, and more particularly, to such an array incorporating flash memory cells.
2. Background Art
One type of programmable memory cell is commonly referred to as the flash memory cell. The structure of one type of flash memory cell includes a source and a drain formed in a silicon substrate. The structure of another type of flash memory cell includes a source and a drain formed in a well that is formed in a silicon substrate. The flash memory cell includes a stacked gate structure formed on the silicon substrate. The region of the silicon substrate beneath the stacked gate structure is known as the channel region of the flash memory cell.
The stacked gate structure of a flash memory cell includes a pair of polysilicon structures separated by oxide layers. One of the polysilicon structures functions as a floating gate and the other polysilicon structure functions as a control gate for the flash memory cell. The oxide layer that separates the floating gate from the silicon substrate is commonly referred to as a tunnel oxide layer.
Programming operations on the flash memory cell involve application of a relatively large constant voltage to the drain of the flash memory cell while an even larger voltage is applied to the control gate. During such programming operation, the source of the flash memory cell is maintained at a ground level or a zero voltage level in relation to the voltages applied to the control gate and drain.
Such a relatively high voltage potential applied between the drain and source causes electrons to flow through the channel region from the source to the drain. The electrons flowing between the source and drain can obtain relatively high kinetic energy levels near the drain. In addition, the high constant voltage applied to the control gate raises the voltage potential of the floating gate to a high level at the start of the programming operation. Such a high voltage potential on the floating gate usually attracts the electrons flowing through the channel region. Under these conditions, electrons in the channel region having sufficiently high kinetic energy migrate through the tunnel oxide layer and onto the floating gate. This phenomenon is commonly referred to as hot carrier programming or hot carrier injection. A successful programming operation involves the injection of sufficient numbers of electrons onto the floating gate to achieve the desired threshold voltage for the flash memory cell. The threshold voltage is the voltage that must be applied to the control gate of the flash memory cell to cause conduction through the channel region during a read operation on the flash memory cell. The time involved in a programming operation depends upon the rate at which electrons are injected onto the floating gate.
The microelectronic flash or block-erase Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) includes an array of cells that can be programmed and read. The size of each cell and thereby the memory are made small by omitting transistors known as select transistors that would enable the cells to be erased independently. As a result, all of the cells must be erased together as a block.
A flash memory device of this type includes individual metal-oxide-semiconductor (MOS) field effect transistor (FET) memory cells. Each of the FETs includes a source, a drain, a floating gate, and a control gate to which various voltages are applied to program the cell with a binary 1 or 0, to read the cells, or to erase all of the cells as a block.
The cells are connected in an array of rows and columns, with the control gates of the cells in a row being connected to a respective word line and the drains of the cells in column being connected to a respective bit line. The sources of the cells are connected together. This arrangement is known as a NOR memory configuration.
A cell is programmed by applying programming voltage as follows: a voltage, typically in the range of 9-10 volts to the control gate, a voltage of approximately 5 volts to the drain and grounding the source. As disscussed above, these voltages cause electrons to be injected from the drain depletion region into the floating gate. Upon removal of the programming voltages, the injected electrons are trapped in the floating gate and create a negative charge therein that increases the threshold voltage of the cell to a value in excess of approximately 4 volts.
A cell is read by applying a voltage of about 5 volts to the control gate, applying about 1 volt to the bit line to which the drain is connected, grounding the source, and sensing the bit line current. If the cell is programmed and the threshold voltages is relatively high (4 volts), the bit line current will be zero or at least relatively low. If the cell is not programmed or erased, the threshold voltage will be relatively low (2 volts), control gate voltage will enhance the channel, and the bit line current will be relatively high.
A cell can be erased several ways. In one arrangement, applying a relatively high voltage, typically 12 volts, to the source, grounding the control gate and allowing the drain to float erases the cell. This causes the electrons that were injected into the floating gate during programming to undergo Fowler-Nordheim tunneling from the floating gate through the thin oxide layer to the source. Applying a negative voltage on the order of xe2x88x9210 volts to the control gate, applying 5 volts to the source and allowing the drain to float can also erase a cell. Another method of erasing a cell is by applying 5 volts to the P-well and xe2x88x9210 volts to the control gate while allowing the source and drain to float.
A problem with conventional flash EEPROM cells is that because of manufacturing tolerances, some cells become over-erased before other cells become sufficiently erased. The floating gates of the over-erased cells are either completely or partially depleted of electrons and having a very low negative charge or become positively charged. The over-erased cells can function as depletion mode transistors that cannot be turned off by normal operating voltages applied to their control gates and introduce leakage current to the bit line during subsequent programming and read operations. The slightly overerased cells can introduce varying amounts of leakage current to the bit line depending on the extent of overerasure.
More specifically, during program and read operations only one word line is held high at a time, while the other word lines are grounded. However, because a positive voltage is applied to the drains of all the cells on the bit line and if the threshold voltage of an unselected cell is very low, zero or negative, a leakage current will flow through the source, channel and drain of the cell.
The undesirable effect of leakage current is illustrated in FIG. 1, which is a simplified electrical schematic diagram of a column 100 of flash EEPROM cells 102, 104, 106, 108. The sources of the column 100 of transistors are all connected to a source supply voltage Vs. A programming or read voltage Vcg, is applied to be control gate of the transistor 104, which turns it on. A current I2 flows through the transistor 104 from ground through the source, channel (not shown) and drain. Ideally, the bit line current Ibl is equal to I2. However, if one or more of the unselected transistors, for example, transistors 102, 106, 108 as illustrated in FIG. 1, are overerased or slightly overerased, their threshold voltages will be very low, zero or even negative, and background leakage currents I1, I3, I4 could flow through the transistors 102, 106 and 108 respectively. The bit line current Ibl would then be equal to the sum of I2 and the background leakage currents I1, I3, I4. In a typical flash EEPROM, the drains of a large number of memory transistor cells, for example 512 transistors cells are connected to each bit line. If a substantial number of cells on the bit line are drawing background leakage current, the total leakage current on the bit line can exceed the cell read current. This makes it impossible to read the state of any cell on the bit line and therefore renders the memory inoperative.
Therefore, what is needed is a memory array wherein leakage cure is reduced.
The present invention is a memory array including a plurality of word lines and a plurality of bit lines. A first transistor is associated with a first word line and is connected in series with a second transistor associated with a second word line. The series-connected first and second transistors are connected between first and second bit lines. A region between the series-connected first and second transistors is connected to the first bit line. A third transistor is associated with third word line and is connected in series with a fourth transistor associated with a fourth word line. The series-connected third and fourth transistors are connected between the second bit line and a third bit line, a region between the series-connected third and fourth transistors being connected to the second bit line. The first, second, third and fourth transistors are respective parts of first, second, third and fourth rows of transistors, while the first and second transistors are part of a first column of transistors, while the third and fourth transistors are part of a second column of transistors.
The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings. As will become readily apparent to those skilled in the art from the following description, there are shown and described embodiments of this invention simply by way of the illustration of the best mode to carry out the invention. As will be realized, the invention is capable of other embodiments and its several details are capable of modifications and various obvious aspects, all without departing from the scope of the invention. Accordingly, the drawings and detailed description will be regarded as illustrative in nature and not as restrictive.